Integrated circuits such as static random access memory (SRAM) circuits and application-specific integrated circuits (ASICs) may require use of two different power supply voltages. For example, an integrated circuit may use a high voltage supply to power high voltage input and/or output circuits such as tri-state buffers, and a low voltage supply to power low voltage internal circuits such as memory cells and logic gates. In this respect, an integrated circuit may use a level shift circuit to translate signals between the high voltage circuits and low voltage circuits.
FIG. 1 is a schematic diagram of a typical level shift circuit 100 that translates a low voltage signal to a high voltage signal. As shown, the level shift circuit 100 may be coupled to a ground voltage supply VSS, a low voltage supply VDDL, and a high voltage supply VDDH.
The level shift circuit 100 may include a first NMOS transistor 102, a second NMOS transistor 104, a first PMOS transistor 106, and a second PMOS transistor 108, each of which is powered by the high voltage supply VDDH. Additionally, the traditional level shift circuit 100 may include one or more inverters 110 that are powered by the low voltage supply VDDL. Additionally yet, the level circuit 100 may have an input node IN that receives low voltage signals, a first output node OE that outputs high voltage signals, and a second output node OEN that also outputs high voltage signals and is complementary of the first output node OE.
As shown, the first NMOS transistor 102 may have a gate coupled to a non-inverted version of the input node IN, a source coupled to the ground voltage supply VSS, and a drain coupled to the first output node OE. As shown, the gate may be coupled to the input node IN through a complementary pair of inverters 110, such that the first NMOS transistor 102 receives a non-inverted version of the input node IN. Alternatively, however, the gate of the first NMOS transistor 102 may be coupled directly to the input node IN. The second NMOS transistor 104 may have a gate coupled to an inverted version of the input node IN, a source coupled to the ground voltage supply VSS, and a drain coupled the second output node OEN. As shown, the gate of the second NMOS transistor 104 may be coupled to the input node IN through a single inverter 110 coupled in series with the input node IN, such that the second NMOS transistor 104 receives an inverted version of the input node IN.
The first PMOS transistor 106 may have a gate coupled to the second output node OEN, a source coupled to the high voltage supply VDDH and a drain coupled to the first output node OE. The second PMOS transistor 108 may have a gate coupled to the first output node OE, a source coupled to the high voltage supply VDDH, and a drain coupled to the second output node OEN.
As a result of the above configuration, the transistors 102, 104, 106, and 108 are cross-coupled. More particularly, the drain of the first NMOS transistor 102, the drain of the first PMOS transistor 106, and the gate of the second PMOS transistor 108 are coupled together at the first output node OE. Similarly, the drain of the second NMOS transistor 104, the drain of the second PMOS transistor 108, and the gate of the first PMOS transistor 106 are coupled together at the second output node OEN. Preferably, the NMOS transistors 102 and 104 will have a larger drive capability than the PMOS transistors 106 and 108.
Operation of the level shift circuit 100 with both the high voltage supply VDDH and the low voltage supply VDDL powered up will now be described. In one example, the input IN node of the level shift circuit may transition from a logic “1” value in the low voltage domain of approximately VDDL to a logic “0” value in the low voltage domain of approximately VSS. As a result, the first NMOS transistor 102 may be disabled and the second NMOS transistor may be enabled, thus pulling the second output node OEN to the ground voltage of approximately VSS. In turn, the first PMOS transistor 106, which has its gate coupled to the second output node OEN, may be enabled. The enabled first PMOS transistor 106 may then pull the first output node OE to a logic “1” value in the high voltage domain of approximately VDDH, thus disabling the second PMOS transistor 108, which has its gate coupled to the first output node OE. As a result, the first output node OE may be stable at a logic “1” value in the high voltage domain of approximately VDDH, and the second output node OEN may be stable at a logic “0” value in the high voltage domain of approximately VSS.
In another example, the input IN node of the level shift circuit may transition from a logic “0” value in the low voltage domain of VSS to a logic “1” value in the low voltage domain of approximately VDDL. As a result, the second NMOS transistor may be disabled and the first NMOS transistor 102 may be enabled, thus pulling the first output node OE to the ground voltage of approximately VSS. In turn, the second PMOS transistor 108, which has its gate coupled to the first output node OE, may be enabled. The enabled second PMOS transistor 108 may then pull the second output node OEN to a logic “1” value in the high voltage domain of approximately VDDH, thus disabling the first PMOS transistor 106, which has its gate coupled to the second output node OEN. As a result, the first output node OE may be stable at a logic “0” value in the high voltage domain of approximately VSS, and the second output node OEN may be stable at a logic “1” value in the high voltage domain of approximately VDDH.
In the level shift circuit 100 described above, a problem may occur if the high voltage supply VDDH is enabled, and thus powering up, while the low voltage supply VDDL is still disabled. In this situation, the output nodes of the level shift circuit 100 may be at unpredictable voltage levels. For example, when the high voltage supply VDDH is powering up and the low voltage supply is the ground voltage VSS, the first output node OE could either be at a high logic “1” voltage of VDDH or a high logic “0” voltage of VSS, regardless of the state of the input node IN. In turn, the second output node OEN, as a complementary node, would be in the opposite state of the first output node OE.
The unpredictable nature of the level shift circuit's output voltage levels described above may be undesirable, especially when the level shift circuit's outputs are controlling a tri-state output buffer that is driving a common bus with additional tri-state buffers. In this respect, if the tri-state output buffer is improperly enabled by the level shift circuit, the tri-state output buffer may force a voltage on the common bus that is opposite to other voltage on the common bus, thus causing a high current condition on the common bus. Accordingly, a level shift circuit that outputs predictable voltage levels when its high voltage supply is powering up and it low voltage supply is disabled, while avoiding DC currents, is desirable.